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agilent hdmp-1032/1034 transmitter/receiver chip set data sheet features ? 3.3 v supply, low power dissipation 590 mw tx, 660 mw rx ? on-chip encode/decode using conditional inversion master transition (cimt) protocol ? 1:n broadcast ready configurable receiver inputs allow multi-point data broadcast using a single transmitter ? parallel automatic synchronization system (pass) allows receiver to read recovered words with local reference clock ? robust simplex mode ? wide range serial rate 260-1400 mbaud (user selectable) ? 5 v tolerant ttl interface 16 or 17 bits wide ? low cost 64 pin plastic package 14x14 mm 2 pqfp applications ? cellular base station ? atm switch ? backplane/bus extender ? video, image acquisition ? point to point data link ? implement sci-fi standard description the hdmp-1032 transmitter and HDMP-1034 receiver are used together to build a high-speed data link for point-to-point communication. these silicon bipolar transmitter and receiver chips are housed in standard plastic 64 pin pqfp packages. from the users viewpoint, these products can be thought of as a virtual ribbon cable interface for the transmission of data and con- trol words. a parallel word loaded into the tx (transmitter) chip is delivered to the rx (receiver) chip over a serial channel and is then reconstructed into its origi- nal parallel form. the channel can be either a coaxial copper cable or optical link the chip set hides from the user the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. the cimt encoding scheme used en- sures the dc balance of the serial line. when data or control words are not being sent the transmitter sends idle words. the serial data rate of the tx/rx link is selectable in three ranges and extends from 208 to 1120 mbit/s. this translates into an encoded serial rate of 260 to 1400 mbaud. the parallel data interface is 16 bit ttl. a flag bit is also present and can be used as an extra 17th bit under the users control. this bit can be used as an even or odd word indicator for dual-word transmission. the encoding of the flag bit can be scrambled to reduce the probabil- ity of erroneous word alignment. a user control space is also provided. if txcntl is asserted on the tx chip, the least signifi- cant 14 bits of the data will be sent and the rxcntl line on the rx chip will indicate the data is a control word. at the rx, the pass feature allows the recovered words to be clocked out with the local 1.4 gbd transmitter/receiver chip set with cimt encoder/decoder and variable data rate.
2 refclk. this feature is particu- larly useful when the tx clock and refclk are synchronous. the pass system also supports synchronization of multiple channels. the chipset is compatible with previous versions of the g-link chipset (hdmp-10x2/10x4) pro- vided the latter are used in 16 bit simplex with periodic sync pulse or external reference oscillator mode (simplex method ii or iii). table of contents topic page typical applications ................................................................................................... 3 setting the operating data rate range .................................................................. 4 transmitter block diagram ....................................................................................... 5 receiver block diagram ............................................................................................ 6 parallel automatic synchronization system .......................................................... 7 transmitter timing .................................................................................................... 10 receiver timing ........................................................................................................... 11 dc electrical specifications ..................................................................................... 12 ac electrical specifications ..................................................................................... 12 txclk and refclk requirements ........................................................................... 13 absolute maximum ratings ...................................................................................... 13 thermal characteristics ............................................................................................ 14 i/o type definitions .................................................................................................... 14 pin-out diagrams ........................................................................................................ 15 transmitter pin definitions ........................................................................................ 16 receiver pin definitions ............................................................................................ 18 mechanical dimensions ............................................................................................ 21 appendix: internal architecture information line code description ................................................................................................ 22 data, control, and idle word codes ........................................................................ 22 tx operation principles C encoding & phase lock loop .................................... 24 rx operation principles C decoding & phase lock loop.................................... 25 integrator capacitor & power supply bypassing/grounding ................................................................................................. 26 ttl and high speed i/o ............................................................................................. 26 data bus line/broadcast transmission ................................................................. 27 nomenclature changes between hdmp-1032/34 and hdmp-1022/24 .......................................................................... 30 pin cross reference table ........................................................................................ 31
3 typical applications the hdmp-1032/1034 chipset was designed for ease of use and flexibility. the customer can tailor the use of this product through the configuration of the link based on specific system re- quirements and application needs. typical applications range from backplane serialization and bus extension to cellular base stations. all modes are built up from the basic simplex transmission mode as shown in figure 1a. for digital video transmission, simplex links are common. the hdmp-1032/1034 chipset can transmit 16 bits of parallel data in standard or broadcast simplex mode (figures 1a, 1b). if the bus is 32 bits wide, the hdmp-1032/1034 chipset is ca- pable of sending this data word as two separate word segments with the use of an external mux and demux as shown in figure 1c. in this mode, the transmitter and receiver use the flag bit to indi- cate the first or second word segment. the hdmp-1032/1034 chipset may also be configured in full duplex to achieve a 32 bit wide bus extension. in addition, 32 bit wide data can be transmit- ted over two parallel serial lines as shown in figure 1d. low latency bus extension of a 16 bit wide data bus may be achieved using the full duplex configuration (figure 1e). in this mode, link startup is achieved by exchange of control words. figure 1. various configurations using the hdmp-1032/1034. tx rx txclk rxclk0/1 a) 16 bit simplex transmission refclk txclk tx rx rxclk0/1 b) 16 bit broadcast transmission rx rxclk0/1 rx rxclk0/1 refclk refclk refclk txclk tx rx rxclk0/1 mux demux c) 32 bit simplex transmission refclk txclk tx rx rxclk0/1 txclk tx rx rxclk0/1 d) 32 bit simplex transmission refclk refclk txclk tx rx rxclk0/1 rxclk0/1 rx tx txclk e) 16 bit duplex transmission refclk refclk
4 hdmp-1032 (tx), HDMP-1034 (rx) typical operating rates 1,2 tc = C20 c to +85 c, v cc = 3.15v to 3.45v parallel word rate serial data rate serial baud rate (mword/sec) (mbits/sec) (mbaud) div1 div0 range range range 0 0 40 70 (max) 640 1120 (max) 800 1400 (max) 0 1 20 45 320 720 400 900 1 0 13 (min) 26 208 (min) 416 260 (min) 520 figure 2. typical data rates showing ranges of operation 1 . notes: 1. all values in this table and graph are typical unless otherwise noted by (min) or (max), (min) indicates a minimum guaranteed value, (max) indicates a maximum guaranteed value. 2. all values in this table are expected for a ber less than 10 -14 . 0/0 0/1 1/0 5 25 50 75 100 2000 1500 1000 500 100 800 400 260 (min.) 520 900 1400 (max.) div 1 / div 0 serial baud rate (mbaud) word rate (mwords/sec) is unique. the user serial data rate is calculated as: the baud rate includes an addi- tional four encoding bits (20 bits total) that the hdmp-1032/34 g-link chipset transmits. the serial baud rate is calculated as: example 2 (overlapping ranges) some applications may have a parallel word rate that seems to fit in two ranges of opera- tion. for example, a 42.5 mhz (42.5 mword/s) parallel data rate falls within two ranges: div1/0 = (0/0) and div1/0 = (0/1). according to the table, a setting of div1/0 = (0/1) gives serial baud rate = (CCCCC) (CCCCC) = 1200 mbaud 20bits word 60mw sec serial data rate = (CCCCC) (CCCCC) = 960 mbits/sec 16bits word 60mw sec setting the operating data rate range the hdmp-1032/1034 chipset can operate from 260 mbaud to 1400 mbaud. it is divided into three operating data ranges with each range selected by setting div1/0 as shown in the typical operating rates table. two examples have been provided in order to help in understanding and using this table. example 1 (unique range) it is desired to transmit a 16 bit parallel word operating at a fre- quency of 60 mhz (60 mword/ sec). both the tx and rx must be set to a range that covers this word rate. according to the table only a setting of div1/0 = (0/0) allows a parallel input word rate of 40 to 70 mhz. this range setting easily accommodates the required 60 mhz word rate and an upper rate of 45 mhz while a setting of div1/0 = (0/0) gives a lower rate of 40 mhz. the upper and lower data rates stated in the tables are typical values unless indicated by (min) or (max) and may vary between individual parts. however, each transmitter/receiver has overlapping ranges of opera- tion providing continuous band coverage from 260 to 1400 mbaud. in this example, each transmitter/ receiver will permit a 42.5 mhz parallel data rate but it is sug- gested that div0 be tied to a jumper that can be set either to logic 1 (open allowing div0 to float high) or logic 0 (ground). this allows the design to accom- modate both ranges for maximum flexibility. this technique is rec- ommended whenever operating near the upper and lower ends of two adjacent word rate ranges.
5 figure 3. hdmp-1032 transmitter block diagram. the c-field logic, based on the inputs at txcntl, txdata, txflgenb and txflag, sup- plies the four bits of the c-field to the encoded word mux. these bits contain information regard- ing the word type: control, data or idle. in order for the txflag bit to be used as an additional data bit, txflgenb must be set high on the tx and rxflgenb must be set high on the rx. if scrambling of the encoding of the flag bit is desired, esmpxenb pin must be set high on both the tx and rx. see flag descrambler section on next page for a more detailed description of the enhanced simplex mode. the w-field logic (word field) presents either bits tx[0-15] or an idle word to the encoded word mux. encoded word mux the word mux accepts the four encoding bits from the c-field and 16 data bits from the w-field. these 20 bits of parallel information are then multiplexed to a serial line based on the internal high-speed serial clock. hdmp-1032 tx block diagram the hdmp-1032 transmitter was designed to accept 16 bit wide parallel words and transmit them over a high-speed serial line. the hdmp-1032 performs the follow- ing functions: ? latching parallel word input ? phase lock to txclk ? high speed clock multiplication ? word encoding ? parallel to serial multiplexing pll/clock generator the phase lock loop and clock generator are responsible for generating all the internal clocks needed by the transmitter to perform its functions. these clocks are based on a supplied word clock (txclk) and control signals (txdiv1/0, tclkenb). txclk is the incoming word clock. the pll/clock generator locks on to this incoming rate and multiplies the word rate clock by 20 (16 word bits + 4 encoding bits). as lock is achieved, locked is set high. the txdiv1/0 pins configure the transmitter to accept incoming data words within the desired frequency range. by setting tclkenb high, the user may provide an external ttl high speed serial clock at txclk. this clock replaces the internal vco clock and is in- tended for diagnostic purposes only. this uncharacterized signal is used directly by the high-speed serial circuitry to output the se- rial data at speeds that are not within the vco range. c-field and w-field encoder logic this logic determines what infor- mation is sent to the encoded word mux. if txcntl is high, the logic sends bits tx[0-13] and a c-field (coding field) encoded as a control word regardless of the state of txdata. if txcntl is low and txdata is high, the logic sends tx[0-15] and a c-field encoded as a data word. if neither txcntl nor txdata is set high, then the transmitter assumes the link is not being used. in this case, the logic sub- mits an idle word to the encoded word mux to maintain the dc balance on the serial link and allow the receiver to maintain frequency and phase lock. c-field encoder txflag tx[0-15] w-field encoder invert word mux txflgenb esmpxenb txclk txdiv1/0 tclkenb locked pll / clock generator accumulate txcap0 txcap1 hsout flag encoder txdata txcntl latch input input latch sign +
6 sign the sign circuitry determines the disparity of the encoded word. disparity is defined as the total number of high bits minus the total number of low bits. accumulator block this block is responsible for keeping track of total disparity of all previously sent words. invert block the invert block is responsible for maintaining the dc balance of the serial line. it determines based on history and the sign of the current encoded word whether the current encoded word should be inverted to bring the serial line closer to the desired 50% duty cycle. HDMP-1034 rx block diagram the HDMP-1034 receiver was designed to convert a serial data signal sent from the hdmp-1032 into either 16 or 17 bit wide parallel data. the HDMP-1034 performs the following functions: ? frequency lock ? phase lock ? encoded word synchronization ? de-multiplexing ? word decoding ? encoding error detection input sampler and clock-data recovery (cdr) in order to compensate for any amplitude distortion present in the serial data signal, the high- speed inputs, hsin , are always equalized. the cdr block locks to the frequency of the refclk and to the phase of the sampled input signal. the recovered data is sent to the demux block and a bit-rate clock is sent to the clock generator block. if the serial data signal is absent, the cdr block will maintain frequency lock onto refclk. figure 4. HDMP-1034 receiver block diagram. the rxdiv1/0 pins select the data rate range by dividing the vco range by 1, 2 or 4. when rxdiv1/0 = 1/1, the internal vco is bypassed and the test clock input tstclk can be used as the serial input. clock generator using the recovered bit-rate clock, the clock generator block generates all of the re- quired internal clocks including the word rate clocks: rxclk0/1. using the word align blocks bit adjust output, the phase of the word-rate clocks is adjusted bit by bit for proper word align- ment. for testing purposes this adjustment function can be disabled using the wsyncdsb input; word alignment can also be forced using the #reset pin. rxready word align sync logic rxerror rxdata rxcntl shfout srqout rxdslip output latch delay rxflag rx[0-15] shfin srqin passenb invert decode flag descrm hsin rxflgenb esmpxenb clock generator demux cdr rxclk0/1 #reset wsyncdsb refclk rxdiv1/0 pass system rxcap1/0 tstclk +
7 when the tx and rx clock are not synchronous, fifos are usu- ally used to cross the frequency domains. the size of the fifo and the frequency difference determine the maximum packet size of transmission. when the clock from the tx is synchronous with the rx clock, data can be transmitted continu- ously without fifos since the parallel output data is synchro- nous with the local refclk. however, due to link distance and other physical variables, the rela- tive phase of the refclk to the recovered data is unpredictable. because of this unknown phase, the sampling of the recovered word must be adjusted so that the internal setup/hold times are not violated. furthermore, in a multi- channel system, the setting of the phase must be consistent so that time slots across the channels are preserved. the pass system was designed to address these issues by sensing the phase difference between the local refclk with the recovered clock, and shifts the phase of the parallel output data with the delay block, such that it can be clocked out with the rising edge static valid code-field bits being embedded within the data-field. enhanced simplex mode can be turned off (esmpxenb=0) to make it compatible with previous versions of g-link. with this mode turned off and txflgenb=1, the flag bit is sent unscrambled to the rx. if txflgenb=0, the flag bit will alternate at the tx. when rxflgenb=0, the rx will use this alternating flag for error checking. parallel automatic synchronization system (pass) as shown in figure 4, this system consists of three blocks: the parallel delay block (delay), the output latch block (output latch), and the synchronization logic block (sync logic). this system was designed to provide a simple interface to the parallel outputs for a synchronous system. background traditionally, the parallel outputs are clocked out with the falling edge of rxclk1 as shown in figure 4.1. since this clock is recovered from the serial data, this clock is synchronous with the remote clock at the tx. demultiplexer (demux) this block takes the recovered serial data from the cdr block and demultiplexes it into a 20-bit parallel word comprised of a 16-bit word-field and 4-bit code-field. decoder (decode) this block decodes the 4-bit code-field and determines whether the 16-bit word-field is: normal or inverted; data, control, or idle words; or errors. the flag bit is also decoded from the data word. word alignment (word align) this block detects the error out- put of the decoder block. upon detecting two consecutive errors, word align requests a bit adjustment to the clock generator (assuming wsyncdsb=0). if enhanced simplex mode is engaged (esmpxenb=1), the word align block looks for a transition in the scrambled flag bit over a window of 32 words. if a transition is not detected, word align requests a bit adjustment to the clock generator (assuming wsyncdsb=0). when the bit adjustment output has been low for 64 up to 128 words, the rxready output goes high. if the bit adjustment output goes high, rxready immediately goes low. flag descrambler (flag descrm) this block descrambles the flag bit if the enhanced simplex mode is engaged (esmpxenb=1); oth- erwise, the flag bit is unaltered. scrambling ensures that the flag bit is dynamic and thus can be detected by the word alignment block. scrambling of the flag bit provides an extra level of protection to guard against im- proper word alignment caused by figure 4.1. traditional g-link configuration with pass disabled (passenb=0). recovered data words and rxclk0/1 are synchronous with txclk. hsout hsin rx tx txclk txclk refclk refclk srqout nc nc srqin shfin shfout rxclk0/1 rx[0-15] nc nc data 16 bits tx[0-15] passenb
8 of the refclk. by adjusting the phase of the data word rather than refclk, the optimal setup time is achieved for the input latches of the chip interfacing to the rx. as the relative phase between the hsin input and the refclk drift slowly over time due to envi- ronmental variations, the pass system is able to absorb this to some degree, and is able to reset and re-optimize the sampling when the margin is exceeded. delay block the parallel delay block has an adjustable delay range of 20% to 80% of the data word. its delay is controlled by the sync logic block. this delay block is used for all of the data bits, flag bit, as well as the status bits. output latch block this block is a bank of positive edge triggered d-flip/flops. the clock is selected by the sync logic block to be either the re- covered clock rxclk1 when the pass system is disabled, or the refclk when the pass system is enabled (passenb=1). sync logic block the sync logic blocks func- tion is to compare the phase of the recovered data to refclk, to set the state of the delay block, to detect when the delay range has been exceeded, and to re- cover with a new delay setting. it is also designed to support a master/slave configuration in a multi-channel environment. when rxready goes high, the optimal delay choice is deter- mined at the shift output shfout: shfout = 0 delay retract shfout = 1 delay extend the actual setting of the delay block is determined with the shift input shfin. when the phase of the refclk drifts to within 10% of the word boundary, the rxdslip output is set high, and a new choice of shfout is chosen. the shift re- quest output sqrout is set high when a rxdslip condition is detected, or if the shift request input srqin goes high. figure 4.2. single channel configuration with pass enabled (passenb=1). recovered data words and rxclk0/1 are synchronous with refclk. hsout hsin rx tx txclk refclk refclk srqout nc srqin shfin shfout rxclk0/1 rx[0-15] data 16 bits tx[0-15] passenb +v cc single channel configuration in a single channel configuration, shfin is simply tied to shfout as shown in figure 4.2. the daisy chaining signal srqin is set low (grounded) and srqout is left unconnected. after rxready goes high, the delay block can absorb a phase variation between the serial input hsin and the refclk a mini- mum of ideally 4 serial bits, or 20% of the word period. this margin is reduced due to finite rise/fall times and setup times of the internal circuitry.
9 a shift request (srqout=1) is issued which propagates to the master. the master again selects an optimum shfout, which sets the delay blocks of all receivers consistently. the phase absorption margin for a multiple channel configuration is the same as the single channel case, less the channel-to-channel skews. figure 4.3. multiple channel configuration with pass enabled (passenb=1). multiple channel configuration the connections for a multiple channel configuration are shown in figure 4.3. the daisy-chain signals srqin and srqout are used to allow each receivers pass system shift requests to propagate to the master, which is the last of the chain. the master then con- trols the shift command shfout, which is tied common to the shfin of each receiver. the first srqin in the chain is grounded; the srqout of the master as well as the shfout outputs of the slave units are left uncon- nected. when the internal parallel data boundary of the master, or any of the slaves come within 10% of the refclk, the rxdslip output is set high by the respective rx, hsout hsin rx (slave) tx txclk refclk srqout srqin shfin shfout rxclk0/1 rx[0-15] data 16 bits tx[0-15] passenb +v cc hsout hsin tx txclk refclk srqout srqin shfin shfout rxclk0/1 rx[0-15] data 16 bits tx[0-15] passenb +v cc hsout hsin tx txclk refclk refclk srqout nc srqin shfin shfout rxclk0/1 rx[0-15] data 16 bits tx[0-15] passenb +v cc rx (slave) rx (master) nc nc
10 figure 5. hdmp-1032 (tx) timing diagram. hdmp-1032 (tx) timing characteristics tc = C20 c to +85 c, v cc = 3.15v to 3.45v symbol parameter unit min. typ. max. t s setup time, for tx[0-15], txdata, txcntl and nsec 2.5 txflag relative to rising edge of txclk. t h hold time, for tx[0-15], txdata, txcntl and nsec 2.5 txflag relative to rising edge of txclk. hdmp-1032 (tx) timing the tx timing diagram is shown in figure 5. under normal opera- tions, the tx pll locks an inter- nally generated clock to the incoming txclk at which time locked is set high. the incom- ing data, tx[0-15], txdata, txcntl, and txflag are latched by this internal clock. the data must be valid for t s before it is sampled and remain valid for a time t h after it is sampled. the setup and hold time param- eters, t s and t h , are referenced to the rising edge of txclk. the start of a word, bit tx[0], in the high speed serial output occurs after a delay of t d after the rising edge of the txclk. the typical value of t d is approximately one clock cycle. t s t h t d w-field c-field txclk tx[0-15] txdata txcntl txflag hsout
11 figure 6. HDMP-1034 (rx) timing diagram. HDMP-1034 (rx) timing characteristics tc = C20 c to +85 c, v cc = 3.15v to 3.45v. typical values are at tc = 25 c, v cc = 3.3v symbol parameter unit min. typ. max. t d synchronous output delay referenced to the falling nsec 0 2.0 3.5 edge of rxclk1, pass system disabled (passenb=0). t dp synchronous output delay referenced to the rising nsec 6.0 6.6 8.0 edge of refclk, pass system enabled (passenb=1). t sk allowable skew between hsin and refclk before nsec 20% word pass system resets, passenb=1. period -0.4 nsec HDMP-1034 (rx) timing the rx timing diagram when rxready=1 is shown in figure 6. the serial data stream is deserialized into a parallel word at 1/20 the serial baud rate. when the pass system is dis- abled (passenb=0), there is a latency delay of two words from the input of the first serial bit of a word to the parallel outputs. the parallel outputs, rx[0-15], rxflag, rxready, rxerror, rxdata, rxcntl and rxdslip are clocked out with the falling edge of rxclk1 and appear after a delay of t d . rxclk1 and its complement rxclk0 are both 50% duty cycle clocks. when the pass system is enabled (passenb=1), the timing of the parallel word is adjusted auto- matically 30% of the word pe- riod so that it can be clocked out with the rising edge of refclk and appear after a delay of t dp . c word 1 w c word 2 w c word 3 w c word 4 w hsin rxclk1 rxclk0 refclk t dp t d rx[0] bit 0 note: w = 16 bit word field, c = 4 bit code field
12 hdmp-1032 (tx), HDMP-1034 (rx) dc electrical specifications tc = C20 c to +85 c, v cc = 3.15v to 3.45v, typical values are at tc = 25 c, v cc = 3.3v symbol parameter unit min. typ. max. v ih,ttl ttl input high voltage level, guaranteed high signal v 2.0 v cc for all inputs. v il,ttl ttl input low voltage level, guaranteed low signal v 0 0.8 for all inputs. v oh,ttl ttl output high voltage level, i oh = -400 m a v 2.2 v cc v ol,ttl ttl output low voltage level, i ol = 500 m a v 0 0.6 i ih,ttl input high current, v in = v cc m a40 i il,ttl input low current, v in = 0 volts m a 600 v ip,h50 h50 input peak-to-peak differential voltage mv 200 v op,bll bll output peak-to-peak differential voltage, mv 1000 terminated with 50 w , ac coupled i cc,tx transmitter v cc supply current ma 180 i cc,rx receiver v cc supply current ma 200 ac electrical specifications tc = 25 c symbol parameter unit min. typ. max. t r,ttl in input ttl rise time, 0.8 to 2.0 volts nsec 2 t f,ttl in input ttl fall time, 2.0 to 0.8 volts nsec 2 t r,ttl out output ttl rise time, 0.8 to 2.0 volts, 10 pf load nsec 3.0 t f,ttl out output ttl fall time, 2.0 to 0.8 volts, 10 pf load nsec 3.0 t r,bll bll rise time, terminated with 50, ac coupled 1 psec 240 t f,bll bll fall time, terminated with 50, ac coupled 1 psec 240 vswr i,h50 h50 input vswr 2:1 vswr o,bll bll output vswr 2:1 t fa transmitter & receiver frequency acquisition time msec 4 at power-on 2 t rx_wa receiver word alignment time words 300 notes 1. rise and fall times are measured between 20% and 80% of the voltage range. 2. frequency acquisition time is independent of div1/div0 data rate range.
13 latency tc = 25 c latency latency definition (word clock cycles) passenb = 0 passenb = 1 tx 1.4 1.4 delay from the rising edge of txclk to the first bit tx[0] in the serial stream rx 2.6 3.0 delay from the first bit rx[0] in the serial stream to the falling edge of rxclk1 (or the rising edge of refclk if the pass system is enabled, passenb=1) link 4.0 4.4 transmit word clock (txclk) and receiver reference clock (refclk) requirements tc = C20 c to +85 c, v cc = 3.15 v to 3.45 v symbol parameter unit min. typ. max. f tol txclk and refclk frequency tolerance ppm -100 +100 (refclk is referenced to txclk) symm symmetry (duty cycle) % 40 60 hdmp-1032 (tx), HDMP-1034 (rx) absolute maximum ratings t a = 25 c except as specified. operation in excess of any one of these conditions may result in permanent damage to the device. symbol parameter unit min. max. v cc supply voltage v -0.5 5.0 v in,ttl ttl input voltage v -0.7 5.5 v in,bll h50 input voltage v 2.0 v cc i o,ttl ttl output source current ma 13 t stg storage temperature c -65 +150 t j junction temperature c 0 +150 t max maximum assembly temperature (10 seconds maximum) c +260
14 hdmp-1032 (tx) thermal characteristics t a = 25 c symbol parameter unit typ. q jc 1 thermal resistance, die to case c/w 8 p d power dissipation, v cc = 3.3 v mw 590 HDMP-1034 (rx) thermal characteristics t a = 25 c symbol parameter unit typ. q jc 1 thermal resistance, die to case c/w 8 p d power dissipation, v cc = 3.3 v mw 660 note: 1. based on independent package testing by hp. q jc for the hdmp-1032 and HDMP-1034 is 50 c/w. q jc is measured on a standard 3" x 3" two layer pcb in a still air environment. in order to determine the actual junction temperature in a given application, use the following formula: t j = t c + ( q jc x p d ), where t c is the case temperature measured on the top center of the package and p d is the power being dissipated. i/o type definitions i/o type definition i-ttl input ttl. floats high when left open. o-ttl output ttl hs_out 50 w matched output driver. will drive ac coupled 50 w loads. all unused outputs should be ac coupled to a 50 w resistor to ground. hs in high speed input c filter capacitor node s power supply or ground
15 figure 7. hdmp-1032 (tx) package layout, top view. figure 8. HDMP-1034 (rx) package layout, top view. a hdmp-1032 lot# tx date code gnd 1 tx[14] 2 tx[15] 3 txcntl 4 txdata 5 txflag 6 nc 7 v cc _ttl 8 gnd_ttl 9 txflgenb 10 esmpxenb 11 locked 12 v cc 13 gnd 14 nc 15 nc 16 48 gnd 47 tx[1] 46 tx[0] 45 nc 44 nc 43 nc 42 nc 41 v cc _ttl 40 gnd_ttl 39 nc 38 nc 37 txclk 36 v cc 35 gnd 34 nc 33 txcap1 v cc _hs 17 gnd_hs 18 hsout? 19 hsout+ 20 nc 21 nc 22 nc 23 v cc 24 gnd 25 txdiv0 26 txdiv1 27 tclkenb 28 nc 29 gnd_a1 30 v cc _a1 31 txcap0 32 64 v cc 63 tx[13] 62 tx[12] 61 tx[11] 60 tx[10] 59 tx[9] 58 tx[8] 57 v cc _a2 56 gnd_a2 55 tx[7] 54 tx[6] 53 tx[5] 52 tx[4] 51 tx[3] 50 tx[2] 49 v cc a HDMP-1034 lot# rx date code gnd_ttl 1 rx[1] 2 rx[0] 3 rxready 4 rxerror 5 rxdslip 6 v cc _ttl 7 gnd_ttl 8 v cc 9 gnd 10 refclk 11 tstclk 12 shfin 13 shfout 14 srqout 15 v cc _hs 16 48 gnd_ttl 47 rx[14] 46 rx[15] 45 rxflag 44 rxdata 43 rxcntl 42 v cc _ttl 41 gnd_ttl 40 v cc 39 gnd 38 rxclk1 37 rxclk0 36 wsyncdsb 35 #reset 34 srqin 33 rxcap1 gnd_hs 17 hsin+ 18 hsin? 19 gnd_hs 20 nc 21 rxflgenb 22 esmpxenb 23 v cc 24 gnd 25 passenb 26 nc 27 rxdiv0 28 rxdiv1 29 v cc _a 30 gnd_a 31 rxcap0 32 64 v cc _ttl 63 rx[2] 62 rx[3] 61 rx[4] 60 rx[5] 59 rx[6] 58 rx[7] 57 v cc _ttl 56 gnd 55 rx[8] 54 rx[9] 53 rx[10] 52 rx[11] 51 rx[12] 50 rx[13] 49 v cc _ttl
16 hdmp-1032 (tx) pin definition user mode options name pin type signal txflgenb 10 i-ttl flag bit mode select: when this input is high, the txflag bit input is sent as an extra 17th data bit during data word transfers. as an example, the flag bit can be used as an even or odd word indicator for 32 bit transmission. the rxflgenb input on the rx chip must be set to the same value as the txflgenb pin. esmpxenb 11 i-ttl enhanced simplex mode enable: enables scrambling of the flag bit encoding. the esmpxenb pin on the rx chip must be set to the same value. this mode should be enabled unless compatibility with previous versions of g-link (i.e. hdmp-1024/1014) is desired desired which dont have this feature. txdata 5 i-ttl transmit data word: this input tells the chip that the user has valid data to be transmitted. when this pin is asserted and txcntl is low, bits tx[0-15] and optionally txflag are encoded and sent as a data word. txcntl 4 i-ttl transmit control word: this input tells the tx chip that the user is requesting a control word to be transmitted. when this pin is asserted, bits tx[0-13] are sent as a control word. if txcntl and txdata are asserted simultaneously, txcntl takes precedence. idle words are transmitted if both txdata and txcntl are low. high-speed serial/parallel i/o hsout+ 20 hs_out serial data output: these pins form a buffer line logic driver, hsout- 19 which is a 50 w terminated pecl compatible output. tx[0] 46 i-ttl word inputs: when sending data words, tx[0-15] are serialized. tx[1] 47 when sending control words, tx[0-13] are serialized. tx[2] 50 tx[3] 51 tx[4] 52 tx[5] 53 tx[6] 54 tx[7] 55 tx[8] 58 tx[9] 59 tx[10] 60 tx[11] 61 tx[12] 62 tx[13] 63 tx[14] 2 tx[15] 3 txflag 6 i-ttl flag bit: when txflgenb is active, this input is sent as an extra data bit in addition to the 16 data word bits. when txflgenb is not asserted, this input is ignored and an alternating internal flag bit is transmitted to allow the rx chip to perform error detection during data word transfers. the flag bit is not sent when a control word is transmitted.
17 hdmp-1032 (tx) pin definition (continued) pll/clock generator name pin type signal txcap0 32 c loop filter capacitor: a 0.1 m f min. loop filter capacitor, c2, must txcap1 33 be connected across txcap0 and txcap1 for all combinations of txdiv1/txdiv0. see figure 12. txclk 37 i-ttl transmit word clock input: when tclkenb is low, this word rate clock input is phase locked and multiplied to generate the high- speed serial clock. when tclkenb is high, the pll is bypassed and txclk becomes the serial clock. txdiv0 26 i-ttl vco divider select: these pins program the vco divider chain to txdiv1 27 operate at full, half or quarter speed. see typical operating rates table and figure 2. locked 12 o-ttl locked to txclk: this pin goes high when the transmit pll achieves frequency lock to the txclk signal. power supply/ground v cc 13 s logic power supply: normally 3.3 volts. this power supply is 24 used for the internal transmitter logic. 36 49 64 v cc _ttl 8 s ttl power supply: normally 3.3 volts. used for all ttl transmitter 41 input and output buffer cells. v cc _hs 17 s serial output power supply: normally 3.3 volts. used for serial output pins. v cc _a1 31 s analog power supply: normally 3.3 volts. used for the analog v cc _a2 57 section. gnd 1 s ground: normally 0 volts. tie to ground. 14 25 35 48 gnd_ttl 9 s ttl ground: normally 0 volts. tie to ground. 40 gnd_hs 18 s serial output ground: normally 0 volts. gnd_a1 30 s analog ground: normally 0 volts. gnd_a2 56 test mode/no connect pins tclkenb 28 i-ttl enable external serial rate clock input: when set high, this input causes the txclk input to be used for the serial transmit clock rather than the internal vco clock. it is intended for diagnostic purposes and normally tied low. nc 7 no connect: these pins should be left unconnected. 15 16 21 22 23 29 34 38 39 42 43 44 45
18 HDMP-1034 (rx) pin definition user mode options/status name pin type signal rxflgenb 22 i-ttl flag bit mode select: when set high, the rxflag bit output is available to the user as an extra 17th data bit. esmpxenb 23 i-ttl enhanced simplex mode enable: enables descrambling of the flag bit encoding. the esmpxenb pin on the tx chip must be set to the same value. this mode should be enabled unless compatibility with previous versions of g-link (i.e. hdmp-1022/1012) is desired which dont have this feature. passenb 26 i-ttl enable parallel automatic synchronization system: the parallel rx data and control words are read out with refclk instead of the incoming words parallel clock. the relative phase of the parallel output bits is internally adjusted so that they are clocked out with the rising edge of the refclk. rxdata 44 o-ttl data word available output: this output indicates that the rx chip word outputs rx[0-15] have a data word. rxcntl 43 o-ttl control word available output: this output indicates that the rx chip word outputs rx[0-13] have a control word. high-speed serial/parallel i/o hsin+ 18 hs_in serial data input hsin- 19 rx[0] 3 o-ttl word outputs rx[1] 2 rx[2] 63 rx[3] 62 rx[4] 61 rx[5] 60 rx[6] 59 rx[7] 58 rx[8] 55 rx[9] 54 rx[10] 53 rx[11] 52 rx[12] 51 rx[13] 50 rx[14] 47 rx[15] 46 rxflag 45 o-ttl flag bit: if both txflgenb and rxflgenb have been asserted, this output indicates the value of the transmitted flag bit which can be used as an extra 17th data bit. link status rxready 4 o-ttl receiver ready: this signal is asserted when the word alignment block has seen error-free code field nibbles for 64 up to 128 consecutive words. when esmpxenb = 1, the toggling of the scrambled flag bit is also checked. rxready is de-asserted upon 2 consecutive errors in the code field or if the toggling of the flag bit is absent when esmpxenb=1. rxerror 5 o-ttl received data error: asserted when a word is received which does not correspond to either a valid data, control, or idle word encoding.
19 HDMP-1034 (rx) pin definition (continued) cdr/clock generator name pin type signal rxcap0 32 c loop filter capacitor: a 0.1 m f min. loop filter capacitor, c2, must rxcap1 33 be connected across rxcap0 and rxcap1 for all combinations of rxdiv1/rxdiv0. see figure 12. refclk 11 i-ttl reference clock input: the rx pll uses this input for frequency lock. in addition, rx[0-15], rxflag, rxdata, rxcntl, rxready, rxerror, and rxdslip are clocked out on the rising edge of refclk when passenb=1. rxdiv0 28 i-ttl vco divider select: these pins program the vco divider chain rxdiv1 29 to operate at full, half, or quarter speed. see typical operating rates table and figure 2. rxclk0 37 o-ttl recovered word-rate clock outputs: these outputs are the pll rxclk1 38 recovered word rate clocks. rx[0-15], rxflag, rxdata, rxcntl, rxready, rxerror, and rxdslip are clocked out on the falling edge of rxclk1 when passenb=0. rxclk0 is the inverse of rxclk1. power supply/ground v cc 9s power supply: normally 3.3 volts. this power supply is used for 24 all the core logic other than the output drivers. 40 v cc _ttl 7 s ttl power supply: normally 3.3 volts. used for all ttl receiver 42 input and output buffer cells. 49 57 64 v cc _hs 16 s high-speed supply: normally 3.3 volts. this supply is used to provide clean references for the high-speed inputs, hsin+ and hsin-. v cc _a 30 s analog power supply: normally 3.3 volts. this supply is used to feed power to the analog section of the chip. gnd 10 s ground: normally 0 volts. tie to ground. 25 39 56 gnd_ttl 1 s ttl ground: normally 0 volts. tie to ground. 8 41 48 gnd_hs 17 s high-speed input ground: when tied to ground, the input 20 impedance of hsin+ and hsin- are each matched to 50 w . in order to obtain high impedance (high-z) inputs for 1:n broadcast applications, 18 k w series resistors to -5 v are recommended. gnd_a 31 s analog ground: normally 0 volts. this ground is used for the analog pll portion of the chip.
20 HDMP-1034 (rx) pin definition (continued) pass system rxdslip 6 o-ttl rx word slip: this output is asserted whenever the phase of the parallel word relative to the reference clock has exceeded the range of the internal delay, which results in a slippage of one word. see discussion of pass system on page 7. shfin 13 i-ttl shift input: this input controls the delay of the parallel bits to be clocked out by refclk when passenb=1. in a single rx configuration, shfin is connected to shfout. in a multiple rx configuration, all shfin are connected to the masters shfout. shfout 14 o-ttl shift output: this output, normally connected to shfin, is generated based on the relative phase between refclk and the internal parallel output bits. srqin 34 i-ttl shift request input: in a daisy chain configuration, this input allows a shift request to be propagated to the master. srqin is connected to the srqout of the previous rx in a multi-receiver configuration. srqout 15 o-ttl shift request output: in a daisy chain configuration, this output is connected to the srqin input of the next receiver. srqout goes high when a srqin=1 or when the relative phase between the refclk and the internal parallel bits requires a shift. test mode/no connect pins tstclk 12 i-ttl external serial rate clock input: when rxdiv1/0 = 1/1, this input is used in place of the normal vco signal, effectively disabling the pll and allowing the user to provide an external serial clock for testing. pin is normally tied to v cc _ttl. #reset 35 i-ttl reset: when this active low input is asserted the word alignment is reset. upon release (low to high) the normal word alignment process is reinstated. pin used for test purposes and is normally tied to v cc _ttl. wsyncdsb 36 i-ttl word sync disable: when high, disables resynchronization to word edge upon errors encountered in the c-field of the incoming encoded word. pin used for test purposes and is normally tied low. nc 21 no connect: these pins should be left unconnected. 27
21 package information item details package material plastic lead finish material 85% tin, 15% lead lead finish thickness 300C800 m m lead skew 0.20 mm max lead coplanarity 0.10 mm max (seating plane method) mechanical dimensions of hdmp-1032/34 dimensional parameter d1/e1 d/e b e l c g a2 a1 a (in millmeters) hdmp-103x 14.00 17.20 0.35 0.80 0.88 0.17 0.25 2.00 0.25 2.35 max tolerance 0.10 0.25 0.05 basic +0.15/ max gage +0.10/ max -0.10 plane -0.05 mechanical dimensions pin #1 id e e1 d d1 e b c a1 a2 l g a hdmp-103x top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
22 line code description the hdmp-1032/1034 line code is conditional invert master tran- sition (cimt) as illustrated in figure 9. the cimt line code uses three types of words: data words, control words, and idle words. idle words are generated internally by the tx when both txdata and txcntl are low. each word consists of a word field (w-field) followed by a coding field (c-field). the c-field has a master transition. users can send arbitrary informa- tion carried by data or control words. the dc balance of the line code is enforced automati- cally by the tx. idle words have a single rising edge at the master transition when operating in non-enhanced simplex mode. the coding definitions are sum- marized in the table on the next page. note that the leftmost bit in each table is the first bit to be transmitted in time, while the rightmost bit is the last bit to be transmitted. data word codes in data word mode, all 16 bits of the tx are transmitted to the rx, along with a flag bit. if txflgenb=1, then the user controls this bit with txflag; otherwise it is internally set to alternate. control word codes in control word mode, 14 bits are transmitted to the rx. the lower 7 bits x0-x6 are sent in the w0-w6 space, and the upper 7 bits x7-x13 are sent in the w9-w15 space. bits w7 and w8 are forced 01 for true, and 10 for inverted control words. the shifting of the word field is for backward compatibility with pre- vious versions of g-links chip sets. idle word and error codes two idle words, iw1a and iw1b are provided. unused word codes are mapped into error states. enhanced simplex mode in this mode (esmpxenb=1), the flag bit is scrambled at the tx and descrambled at the rx. since the rx uses the scrambled flag bit for frame alignment, it is also defined for control and idle words. however, the flag bit is only available to the user in the data word mode. the first bit w0 is also scrambled to aid word alignment. figure 9. hdmp-1032/1034 (tx/rx pair) line code. appendix: internal architecture information word field 16 bits coding field 4 bits idle word serial bit stream word k word k+1 master transition master transition
23 coding 1 with esmpxenb=0 (compatible with previous g-link chips, hdmp-1012/14, hdmp-1022/24) word type flag w-field c-field w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 c0 c1 c2 c3 data word structure data = true 0 x0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x151 1 0 1 data = inverted 0 #(x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15) 0 0 1 0 data = true 1 x0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x151 0 1 1 data = inverted 1 #(x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15) 0 1 0 0 control word structure control = true x0 x1 x2 x3 x4 x5 x6 0 1 x7 x8 x9 x10 x11 x12 x13 0 0 1 1 control = inverted #(x0 x1 x2 x3 x4 x5 x6) 1 0 #(x7 x8 x9 x10 x11 x12 x13) 1 1 0 0 idle word structure idle word 1a 1111111110000 00 00011 idle word 1b 1111111000000 00 00011 detectable error states ddddddddddddd dd dd00d ddddddddddddd dd dd11d ddddddd0ddddd dd d1100 ddddddd11dddd dd d1100 ddddddddddddd dd d1010 ddddddddddddd dd d0101 coding 1 with esmpxenb=1 word type flag 2 w-field c-field w0 3 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 c0 c1 c2 c3 data word structure data = true 0 x0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x151 1 0 1 data = inverted 0 #(x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15) 0 0 1 0 data = true 1 x0x1x2x3x4x5x6x7x8x9x10x11x12x13x14x151 0 1 1 data = inverted 1 #(x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15) 0 1 0 0 control word structure control = true 0 x0x1x2x3x4x5x6 0 1 x7x8x9x10x11x12x130 0 1 1 control = inverted 0 #(x0 x1 x2 x3 x4 x5 x6) 1 0 #(x7 x8 x9 x10 x11 x12 x13) 1 1 0 0 control = true 1 x0x1x2x3x4x5x6 0 1 x7x8x9x10x11x12x130 1 0 1 control = inverted 1 #(x0 x1 x2 x3 x4 x5 x6) 1 0 #(x7 x8 x9 x10 x11 x12 x13) 1 0 1 0 idle word structure idle word 1a 0 1111111110000 00 00011 idle word 1b 0 1111111000000 00 00011 idle word 1a 1 1111111110000 00 00101 idle word 1b 1 1111111000000 00 00101 detectable error states ddddddddddddd dd dd00d ddddddddddddd dd dd11d ddddddd0ddddd dd d1100 ddddddd11dddd dd d1100 notes: 1. xi denotes txi or rxi pin, # indicates inversion, d denotes don't care cases. 2. flag bit is scrambled prior to sending. it is only available to the user in data word mode. 3. w0 is scrambled during transmission to further enhance word alignment.
24 tx operation principles the hdmp-1032 (tx) is imple- mented monolithically in a high performance 25 ghz f t silicon bipolar process. the tx performs the following functions for link operation: ? latching parallel word input ? phase lock to txclk ? high-speed clock multiplication ? word encoding ? parallel to serial multiplexing in normal operation, the tx phase locks to a user supplied word rate clock and multiplies the frequency to produce the high-speed serial clock. the tx can accept either 16 or 17 bit wide parallel data and produce a 20 bit encoded word. similarly, 14 bit control words can be transmitted in a 20 bit encoded word. tx encoding a simplified block diagram of the transmitter is shown in figure 3. the pll/clock generator locks onto the incoming word rate clock and multiplies it up to the serial clock rate. it also generates all the internal clock signals required by the tx chip. the data inputs, tx[0-15], as well as the control signals; txdata, txcntl and txflag are latched in on the rising edge of an internally generated word rate clock. the word field is then encoded depending on the state of the txdata and txcntl signals. at the same time, the coding field is generated. at this point, the entire word has been constructed in parallel form and its sign is determined. this word sign is compared with the accu- mulated sign of previously trans- mitted bits to decide whether to invert the word. if the sign of the current word is the same as the sign of the previously transmitted bits, then the word is inverted. if the signs are opposite, the word is not inverted. no inversion is performed if the word is an idle word. the word field and coding field are encoded depending on txdata, txcntl, txflag, txflgenb as well as two inter- nally generated signals, o/e and accmsb. when txflgenb is high and esmpxenb is low, o/e is equivalent to txflag. this is equivalent to adding an addi- tional bit to the data field. when txflgenb is also low, o/e alternates between high and low for data words. this allows the link to perform more extensive error detection when the extra bit is unused. accmsb is the sign of the previ- ously transmitted data. this is used to determine which type of idle word should be sent. when accmsb is low, iw1a is sent and when accmsb is high, iw1b is sent. this effectively drives the accumulated offset of transmitted bits back toward the balanced state. tx phase-lock loop the block diagram of the trans- mitter phase-lock loop (pll) is shown in figure 10. it consists of a sequential frequency detector, loop filter, vco, clock generation circuitry and a lock indicator. the outputs of the frequency detector pass through a charge pump filter that controls the center frequency of the vco. figure 10. hdmp-1032 (tx) phase-lock loop. frequency detector txclk clock generator lock detect divide by n loop filter vco tstclken txclk 1 0 txdiv1/0 internal clocks external cap
25 an external serial clock can be used instead of the vco clock. this is accomplished by setting tclkenb high and applying a serial rate clock to txclk. note that this mode is used for diagnostic purposes only. one of three frequency bands may be selected by applying the appropriate values to txdiv1/0. the vco or txclk frequency is divided by n where n is 1, 2, or 4 based on the settings of txdiv1/0 as shown in the table below. this divided version of the vco clock or txclk is used as the serial rate clock. n txdiv1 txdiv0 10 0 20 1 41 x rx operation principles the HDMP-1034 (rx) is imple- mented monolithically in a high performance 25 ghz f t silicon bipolar process. the rx accepts a serial stream of 20 bit condi- tional invert with master transi- tion (cimt) line code words and outputs parallel 16 bit/17 bit data words or 14 bit control words. the rx performs the following functions for link operation: ? frequency lock ? phase lock ? word synchronization ? demultiplexing ? word decoding ? error detection ? automatic parallel word phase adjustment rx data path figure 4 shows a simplified block diagram of the receiver. the data path consists of an input sampler, a word demultiplexer, a coding field (c-field) decoder, and a word field (w-field) decoder. an on-chip phase-lock loop (pll) is used to extract timing reference from the serial input (hsin ). the pll includes a phase-frequency detector, a loop filter, and a voltage con- trolled oscillator (vco). all the rx internal clock signals are gen- erated from a clock generator that is driven by either the inter- nal vco or an external signal, tstclk, depending on whether both rxdiv1/0 are set high. rx phase-lock loop a detailed block diagram for the rx phase lock loop is shown in figure 11. a frequency detector locks the vco to the reference clock. once this is achieved, a lock indication engages the phase detector, which maintains phase lock of the high speed in- coming bits to that of the internal bit clock. the integrator, which requires one external capacitor, controls the frequency of the vco. the output of the vco is fed into a range selector block, which further divides the vco clock to the bit rate clock. the rxdiv1/0 inputs select between divide by 1, 2, or 4 ranges, as well as a test clock bypass mode. the bit rate clock then drives the clock gen- erator, which provides clocks to the entire chip. rx decoding in figure 4, the word demultiplexer de-serializes the recovered serial data from the input sampler, and outputs the resulting parallel data one word at a time. every word is composed of a 16-bit word field (w-field) and a 4-bit coding field (c-field). the c-field (c0-c3) together with the two center bits of the w-field (w7 and w8) are then decoded by the c-field decoder to determine the content of the word. the w-field decoder is controlled by the outputs of the c-field de- coder. if an inverted data word or control word is detected, the w-field decoder will automati- cally invert the w-field data. if a control word is detected, the w-field decoder will shift the bottom half of the w-field so that the outputs are at pins rx[0-13]. rxdata = 1 indicates that data word is detected by the receiver. rxcntl = 1 indicates that a control word is detected by the receiver. an idle word is detected by the receiver if rxdata = 0, rxcntl = 0, and rxerror = 0. figure 11. HDMP-1034 (rx) phase-lock loop. 0 1 hsin phase detector loop filter vco rxdiv1/0 frequency detector internal clocks refclk external cap divide by n clock generator tstclk internal clocks lock
26 integrator capacitor and supply bypassing/grounding figure 12 shows the pll inte- grator capacitors, power supply capacitors and required ground- ing for the tx and rx chips. integrator capacitor an integrator capacitor (c2) is required by both the tx and rx for them to function properly. this cap is used by the pll for frequency and phase lock, and di- rectly sets the stability and lockup times. a 0.1 m f capacitor is recom- mended for each div1/0 setting. supply bypassing/grounding the hdmp-1032/34 chipset has been tested to work well with a single power plane, assuming that it is a fairly clean power plane. as a result, all of the separate power supplies (v cc , v cc _ttl, and v cc _hs) can be connected onto this plane. the bypassing of v cc to ground should be done with a 0.1 m f capacitor (c1). ttl and highspeed i/o i-ttl and o-ttl these i/o pins are ttl compatible. a simplified schematic diagram of the i/o cells is shown in figure 13. high-speed interface: hs_in and hs_out the simplified schematic diagrams of hs_in and hs_out are shown in figure 14. the hs_in input cell is implemented with internal 50 w resistors between the differential input lines hsin to gnd_hs. the hsin inputs have internal bias provided and the signals are ac coupled in with 0.1 m f capaci- tors. it is recommended that differential signals be applied across the hsin inputs (figure 15a), although a single-ended connection is acceptable. in this case, the unused input must be terminated with 50 w ac coupled to ground. the hs_out output cell is designed to deliver pecl swings directly into 50 w . the output impedance is matched to 50 w and has a vswr of less than 2:1 to above 2 ghz. this output is ideal for driving the hs_in input through a 50 w cable and a 0.1 m f coupling capacitor. the hs_out driver can also be figure 12. hdmp-1032 (tx) and HDMP-1034 (rx) power supply pins. c1 c1 = bypass capacitor c2 = pll integrator capacitor 0.1 ? 0.1 ? v cc _a1 hdmp-1032 tx c1 c1 c1 c1 c2 c1 c1 c1 c1 v cc _a2 c1 note: v cc _a pins supply voltage should come from a low noise source. v cc _a HDMP-1034 rx c1 c1 c2 c1 c1 c1 c1 c1
27 connected directly into a high- speed 50 w oscilloscope. for opti- mum performance, both outputs should see the same impedance. it is necessary that all hs_out outputs be terminated into 50 w . figure 15 shows various methods of interfacing hs_out to hs_in and standard pecl logic. data bus line/broadcast transmission the gnd_hs pins are normally tied to ground to provide 50 w in- put impedance. for 1:n broadcast applications, 18k w series resistors can be inserted between gnd_hs and -5v to provide an effective high impedance as shown in figure 16. a port- bypass circuit (pbc) can also be used in a broadcast application as shown in figure 17. each input and output pbc is a dedi- cated channel and impedance matched to the transmission line. this is a superior method of achieving a broadcast mode com- pared to figure 16, but does add an additional ic. more receivers can be added by cascading pbc ics or using a pbc with more ports. figure 13. o-ttl and i-ttl simplified circuit schematic. v cc _ttl o_ttl i_ttl v cc gnd 1.4 v gnd_ttl gnd v cc esd protection esd protection figure 14. hs_out and hs_in simplified circuit schematic. 50 w v cc hs_in 0.1 f gnd gnd v cc 50 w zo = 50 w hs_out gnd_hs esd protection esd protection 0.1 f
28 figure 15. methods of interfacing hs_out and hs_in. tx hdmp-1032 rx HDMP-1034 50 w 50 w a) g-link tx to rx interconnection hsout+ hsout hsin+ hsin 0.1 f 0.1 f note that no external terminations or bias resistors are required. r2 r1 +v cc 0.1 f pecl input tx hdmp-1032 z0 z0 b) differential drive to generic pecl input hsout+ hsout 0.1 f 0.1 f the thevenin equivalent resistance is equal to the transmission line impedance (z0) and provides proper dc bias to the pecl inputs. r2 r1 + _ 191 w 68 w +5 v 0.1 f optical transceiver (+5 v) tx hdmp-1032 50 w 50 w d) g-link interface to optical transceiver hsout+ hsout 0.1 f 0.1 f 191 w 68 w 270 w rx HDMP-1034 50 w 50 w hsin+ hsin 0.1 f 0.1 f 270 w rd+ rd td+ td pecl output rx HDMP-1034 z0 z0 c) generic pecl output to g-link rx input hsin+ hsin 0.1 f 0.1 f resistor value r1 sets proper bias for the pecl output stage. the g-link rx is internally terminated and doesn't require external bias or termination resistors. r1 r1
29 figure 16. data bus line transmission. figure 17. broadcast transmission using a hdmp-0450 port-bypass circuit. 0 1 1 to_node[1] rx #1 HDMP-1034 fm_node[1] 0 1 2 to_node[2] rx #2 HDMP-1034 fm_node[2] bypass[1]- = 0 0 1 3 to_node[3] rx #3 HDMP-1034 fm_node[3] bypass[2]- = 0 0 1 4 to_node[4] rx #4 HDMP-1034 fm_node[4] bypass[3]- = 0 0 1 to_node[0] rx #5 HDMP-1034 fm_node[0] bypass[4]- = 0 bypass[0]- = 1 tx #1 hdmp-1032 hdmp-0450 0 rs 0.1 ? tx hdmp-1032 hsout+ hsout 0.1 f 0.1 f notes: rs (damping resistor) = 50 w rb (bias resistor) = 18 k w zstub = 50 w or higher, and no longer than 2.54 cm (1 inch) rs 50 w 0.1 ? rx #1 HDMP-1034 rb ? v 20 zstub rb 17 ? v rs 0.1 ? rs 50 w 0.1 ? rx #2 HDMP-1034 rb ? v 20 zstub rb 17 ? v rs 0.1 ? rs 50 w 0.1 ? rx #n HDMP-1034 rb ? v 20 zstub rb 17 ? v 50 w 100 w the 18 k w resistor to ? v bias the rx input and allow high-impedance rx inputs for 1:n broadcast applications.
30 nomenclature changes between hdmp-1032/34 and hdmp-1022/24 in previous versions of g-link such as the hdmp-1022/24 each parallel unit of data was called a frame. this has been changed to a word with the hdmp-1032/34. frame usually stands for a series of words that form a logical unit. for example, each unit of ppp unit is called a frame. it consists of a header and a checksum at the end. the encoded 20 bit entity for the hdmp-1022/24 was composed of a data field and also a control field. this was confusing because the data field contained data frames and control frames. in other words control and data were used in two different con- texts which left the reader to identify which of the two mean- ings was meant. the encoded word was split into a word field and an encoding field. with the hdmp-1032/34 we have: ? control words ? data words ? word field ? ? where one may find control words or data words ? encoding field in addition with the hdmp-1032/ 34, fill frames have been changed to idle words following the custom used in fibre channel and giga- bit ethernet where idles are in- serted if no information is being fed to the transmitter. pin names have been changed to specify if they belong to the transmitter (tx) or the receiver (rx). in addition, some names have been changed to names analogous to those used in fibre channel and gigabit ethernet. examples are txclk instead of strbin and rxclk instead of strbout. a pin cross reference table for the hdmp-1032/34 & hdmp-1022/24 is provided in the table on the next page.
31 caution: as with all semiconductor ics, it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (esd). pin cross reference table hdmp-1032 (tx) hdmp-1022 (rx) pin name name 1 gnd 2 tx[14] d14 3 tx[15] d15 4 txcntl cav* 5 txdata dav* 6 txflag flag 7nc 8 vcc_ttl 9 gnd_ttl 10 txflgenb flagsel 11 esmpxenb 12 locked 13 vcc 14 gnd 15 nc 16 nc 17 vcc_hs 18 gnd_hs 19 hsout- dout* 20 hsout+ dout 21 nc 22 nc 23 nc 24 vcc 25 gnd 26 txdiv0 div0 27 txdiv1 div1 28 tclkenb ehclksel 29 nc mdfsel 30 gnd_a1 31 vcc_a1 32 txcap0 cap0b 33 txcap1 cap1b 34 nc 35 gnd 36 vcc 37 txclk strbin 38 nc 39 nc 40 gnd_ttl 41 vcc_ttl 42 nc 43 nc 44 nc 45 nc 46 tx[0] d0 47 tx[1] d1 48 gnd 49 vcc 50 tx[2] d2 51 tx[3] d3 52 tx[4] d4 53 tx[5] d5 54 tx[6] d6 55 tx[7] d7 56 gnd_a2 57 vcc_a2 58 tx[8] d8 59 tx[9] d9 60 tx[10] d10 61 tx[11] d11 62 tx[12] d12 63 tx[13] d13 64 vcc HDMP-1034 (rx) hdmp-1024 (rx) pin name name 1 gnd_ttl 2 rx[1] d1 3 rx[0] d0 4 rxready linkrdy* 5 rxerror error 6 rxdslip 7 vcc_ttl 8 gnd_ttl 9 vcc 10 gnd 11 refclk 12 tstclk tclk 13 shfin 14 shfout 15 srqout 16 vcc_hs 17 gnd_hs 18 hsin+ din 19 hsin- din* 20 gnd_hs 21 nc 22 rxflgenb flagsel 23 esmpxenb 24 vcc 25 gnd 26 passenb 27 nc tclksel 28 rxdiv0 div0 29 rxdiv1 div1 30 vcc_a 31 gnd_a 32 rxcap0 cap0b 33 rxcap1 cap1b 34 srqin 35 #reset 36 wsyncdsb 37 rxclk0 strbout 38 rxclk1 39 gnd 40 vcc 41 gnd_ttl 42 vcc_ttl 43 rxcntl cav* 44 rxdata dav* 45 rxflag flag 46 rx[15] d15 47 rx[14] d14 48 gnd_ttl 49 vcc_ttl 50 rx[13] d13 51 rx[12] d12 52 rx[11] d11 53 rx[10] d10 54 rx[9] d9 55 rx[8] d8 56 gnd 57 vcc_ttl 58 rx[7] d7 59 rx[6] d6 60 rx[5] d5 61 rx[4] d4 62 rx[3] d3 63 rx[2] d2 64 vcc_ttl
www.semiconductor.agilent.com data subject to change. copyright ? 2000 agilent technologies, inc. 5968-5909e (2/00)

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